Sources and References: INP Device Production
1. Semiconductor Process Control Literature
SEMI E44: Guide for Procurement of Fab Environmental Systems (focus on air stability, humidity, cleanliness).
SEMI E89: Specification for Airborne Molecular Contamination in Cleanrooms.
2. Photonic Integration Research Papers
Peer-reviewed publications demonstrating thermal sensitivity in InP-based PICs:
V. Van et al., Thermal Sensitivity of InP-Based Ring Resonators, IEEE Photonics Tech Letters, 2007.
L. Carroll et al., Temperature Dependence of InP Photonic Devices, Journal of Lightwave Technology, 2015.
These studies show resonant wavelength shifts of 8–10 pm/°C, implying ~0.1–1 pm shifts from ±0.01 °C control.
3. Metrology and Lithography System Specs
Public data sheets from manufacturers such as:
ASML (DUV/EUV lithography tools with ±0.1 °C to ±0.01 °C thermal stability for <30 nm overlay).
Raith/Elionix (e-beam writers that detail mechanical drift vs. temperature).
Bruker AFM and Keysight metrology tools that specify ambient and stage temperature sensitivities in nm/°C or pm/°C.
4. Thermal Expansion Coefficient DatA FOR INP
The equation ~4.6 × 10⁻⁶ /°C guides estimates of mechanical/optical drift from temperature changes.
Example: a 100 mm InP wafer expands ~460 nm per °C; ±0.01 °C yieldig ~4.6 nm change, justifying overlay and bonding drift estimates.
5. Industrial Case Studies and Whitepapers
Cleanroom engineering firms (e.g., Tropel, TSI, Camfil Farr) provide whitepapers with real-world data showing:
Improvements in stage drift, overlay, and yield from upgrading to tighter thermal zoning.
Intel and IBM fabs have historically used sub-±0.05 °C air control to support advanced litho and bonding.
6. Summary of Data Nature
Metric Basis of Estimate
Overlay alignment drift Tool vendor specs + thermal expansion.
Photonic loss (dB) Experimental trends in PIC alignment.
Resonator drift (pm/hr) Literature on dn/dT and Δλ/ΔT.
Stage drift (nm/hr) Metrology OEM datasheets.
7. Caveat
Exact quantitative values can vary by:
Tool architecture.
InP layer stack and thermal budget.
Fab environment and integration strategy.